A large variety of thin films are used in the fabrication of semiconductor devices. The uniformity of a wafer must be tightly maintained throughout the entire fabrication process in order to allow increasingly fine and microscopic geometric features to be precisely formed. Every layer deposited on the top surface of the wafer that possesses irregularities and variations in its uniformity has an adverse effect during subsequent processing steps that the %wafer undergoes. Uniformity of the layers is a critical factor in semiconductor wafer production. It is, therefore, important that the wafer surface be as clean as is technically possible before each fabrication step in order to obtain the precision and high yields in semiconductor fabrication. To accomplish these fabrication goals, *wet process wafer cleaning and/or wet etching procedures are carried out prior to many of the process steps.
When a silicon wafer is chemically cleaned prior to a furnace or baking step, a widely used cleaning technique includes the RCA method or RCA clean (RCA Review, pp. 187-206 (June, 1970)). The conventional RCA clean is, for example, conducted at high temperature and includes use of a first cleaning solution, Standard Clean 1 (SC1) consisting of a dilution of ammonium hydroxide/hydrogen peroxide (NH.sub.4 OH/H.sub.2 O.sub.2) followed by a deionized (DI) water rinse. Then, a second cleaning solution, Standard Clean 2 (SC2) which is a hydrochloric acid/hydrogen peroxide (HCL/H.sub.2 O.sub.2) dilution is used and a second DI water rinse is performed. The PICA clean provides a chemical oxide passivated wafer surface.
Another wet cleaning method that has been recently used as an alternative to the RCA clean is the Baker clean. The Baker clean is a relatively short two-step process, instead of the longer, for example, four step RCA clean. The Baker clean uses a proprietary cleaner, JTB-100 (J. T. Baker Microelectronics, Mallinckrodt Baker, Inc., Phillipsburg, N.J.) and a single DI water rinse. The JTB-100 contains tetra methyl ammonium hydroxide (TMAH) and is designed to be used in conjunction with H.sub.2 O.sub.2 The Baker clean appears to have improvements over the RCA clean in terms of simplicity, decreased impurity levels and chemical stability in the cleaning bath.
There are also other wet cleaning methods utilized, such as, for example, the Piranha clean which uses sulfuric acid (H.sub.2 SO.sub.4) based mixtures. For example, the sulfuric acid may be used with hydrogen peroxide.
Although the above described cleaning techniques are widely utilized, wet etching or surface conditioning of silicon dioxide (SiO.sub.2) films in semiconductor fabrication processes, is usually accomplished by hydrofluoric acid (HF) cleaning, such as by immersion in HF solutions, spraying with HF solutions, or treatment by HF vapors. As is known to one skilled in the art, a thin oxide grows on silicon when it is exposed to air. This thin oxide, known as native oxide, can adversely affect subsequent fabrication steps. The HF wafer cleaning removes the native oxide from the surface and provides a hydrogen passivated oxide free silicon surface which is desirable prior to many process steps. The HF cleaning may be performed before, after, or between cleaning steps performed with other solutions or vapors, such as with the RCA clean, to remove native oxide and pros ide a hydrophobic oxide free surface.
However, HF cleans, while etching native oxide, also etch other commonly formed regions of the wafer, for example, doped or deposited oxides such as borophosphosilicate glass (BPSG) and tetraethylorthosilicate (TEOS) based oxides. These other formed regions are etched to quickly relative to the removal of native or thermal oxides for accomplishing adequate process control and which may cause difficulty in process integration. As the doping in deposited oxides increases, the etching of such oxides occurs even faster relative to native or thermal oxides, further increasing process control problems.
In addition, with the use of cluster-based tools and processes, the demand for in situ cleaning which is integrated into a multi-purpose module for use in the cluster tool increases. The use of HF vapor clean is a process that would be beneficial for use in cluster tools. However, in the HF vapor clean, the etching of thermal or doped oxides is even faster relative to the etching of thermal or native oxide than with the use of an HF solution clean.
Therefore, the etch selectivity ratio of deposited or doped oxides to thermal or native oxide is considerably high and inadequate in many circumstances when using conventional HF clean methods and solutions/vapors utilized therewith. Such ratios for HF vapor cleans have been shows to be as low as 4:1 and 5:1 as described in the FSI "Technical Report DC/DE -Dry Cleaning/Dry Etching," FSI International, Chaska, Minn. (1990). This article appears to indicate that such ratios are achieved by changing the initiation of the etch reaction using increased amounts of water vapor in the HF vapor to initiate the thermal or native oxide removal faster.
Further, the use of HF cleans also has the disadvantage of providing poor wettability on the wafer surface and contributes to surface microroughness. With increasing fine geometries and patterns fabricated into the wafers, as for example with high aspect ratio contact holes, conventional HF solutions are not as effective in cleaning the silicon surfaces at the bottom of such patterns.
As described above, the etch selectivity ratio of two different oxides is of importance when applying an etch process to a wafer surface. This is of particular importance when the objective is to remove small amounts of native oxide, for example, from a silicon contact area or any other active area, yet limit the etching of an adjacent oxide, such as a deposited or doped oxide, which normally has a higher etch rate than the native oxide. Therefore, improvements in the currently available cleaning processes are needed to improve the effectiveness of the wafer clean, and particularly to reduce the etch selectivity ratio of etching other wafer regions, such as doped oxides, to the etching of thermal or native oxides.